1. Field of the Invention
The present invention relates to a semiconductor device and a wiring method and, more particularly, to a semiconductor device that is preferred as for a bit line control circuit in a memory and a wiring method for such semiconductor device.
2. Description of the Related Art
A Static Random Access Memory (SRAM) is a semiconductor memory that can operate at a high speed and, therefore, is used widely as a register or cache memory inside a central processing unit (CPU). In recent years, there has been an increasing demand for larger storage capacity and faster reading of the memory.
Each memory cell in a SRAM is connected with one word line and one bit line pair BL and BLB and, when the word line is set to “1”, bit data is read and written via the bit line pair BL and BLB. The read operation, which is required to be faster, is typically performed by using a sense amplifier to amplify a small potential difference between BL and BLB in accordance with the value of the memory cell. (see Japanese Unexamined Patent Publication No. 2003-109379.)
The following approaches have been adopted in the related art so that the small potential difference between the bit lines can accurately reflect the value of the memory cell. One approach is to precharge both of the bit lines to High potential before the bit data is read by using two PMOS (Positive-channel Metal-Oxide Semiconductor) transistors, i.e, prechargers that can connect each bit line to the power supply voltage VDD. Another approach is to set both of the bit lines to the same potential by using one PMOS transistor, i.e. an equalizer, that can connect the bit lines with each other.
However, as the density of the memory cells is increased to increase the storage capacity, a load capacitance is also increased and, as a result, the voltage between the bit lines is reduced and any change becomes smaller. Therefore, if there is an variation in the load capacitance between the bit lines, stored data cannot be read accurately. In other words, the load capacitance values of BL and BLB must be exactly equal to each other so that a small voltage between BL and BLB can reflect the value of the memory cell. Thus, the load capacitance values of BL and BLB must be equal to each other to produce the SRAMs at a high yield.
In this connection, in order to prevent imbalance of the load capacitance due to mask deviations when wiring of the SRAM is formed, there has been proposed a technique to exchange positions halfway along two bit lines. (see Japanese Unexamined Patent Publication No. H02-89360.)